Digital signal delay device

ABSTRACT

The invention relates to a digital signal delay device ( 101 ) for converting a signal (IN) into a corresponding delayed signal (OUT), comprising a plurality of signal delay elements ( 103   a,    103   b,    103   c ) connected in series, wherein, as a function of the desired delay of the delayed signal (OUT), the output signal of a particular signal delay element ( 103   a,    103   b,    103   c ) is used for generating the delayed signal (OUT), and wherein the signal delay elements ( 103   a,    103   b,    103   c ) each comprise one single inverter ( 105, 106, 107 ) only.

[0001] The invention relates to a digital signal delay device inaccordance with the preamble of claim 1.

[0002] In semiconductor elements, delay lock loops are often used forgenerating the internal clock. These consist e.g. of many delay membersthat are connected in series.

[0003] A delay member serves to apply a delay to a digital signalavailable at the input of the delay member, so that a digital outputsignal may be tapped at the output of the delay member, said outputsignal being delayed vis-à-vis the input signal, but corresponding to itotherwise.

[0004] A delay member may e.g. consist of two inverters connected inseries, in particular CMOS inverters. The input of the first inverterforms the input, and the output of the second inverter forms the outputof the delay member, the output of the first inverter being connected tothe input of the second inverter.

[0005] When the state of the signal available at the input of the delaymember or of the first inverter, respectively, changes, e.g. from“logically low” to “logically high” (—or vice versa from “logicallyhigh” to “logically low”—), the signal at the output of the firstinverter (and accordingly also the signal at the input of the secondinverter) changes—after a predetermined delay time t_(a)—its state from“logically high” to “logically low” (—or vice versa from “logically low”to “logically high”—).

[0006] Consequently, the signal at the output of the second inverter orat the output of the delay member, respectively, changes—again after apredetermined delay time t_(b)—its state from “logically low” to“logically high” (—or vice versa from “logically high” to “logicallylow”—).

[0007] The signal at the output of the delay member thus corresponds tothe signal at its input, with the exception that it is delayed vis-à-visthereto by a—total—signal delay time of T=t_(a)+t_(b).

[0008] To provide an element or a signal delay device, respectively,with adjustable signal delay time, a plurality of delay members of theabove-mentioned type may be connected in series.

[0009] The signal at the output of the n-th delay member is delayed byn×T vis-à-vis the signal at the input of such a signal delay device.

[0010] The outputs of the delay members may—except with the respectivelyfollowing delay member—additionally be connected with the (total) outputof the signal delay device, e.g. by means of corresponding transfergates.

[0011] By means of the transfer gates, that delay member may beselected, the output signal of which is to be connected through to theoutput of the signal delay device.

[0012] This way, the delay of the (total) output signal can be adjustedwith respect to the signal available at the input of the signal delaydevice or at its first delay member, respectively.

[0013] By means of a signal delay device of the above-mentioned type,the total signal delay which is applied to the input signal is, however,adjustable with relatively coarse exactness only.

[0014] It is an object of the invention to provide a novel digitalsignal delay device.

[0015] This and further objects of the invention are achieved by thesubject matter of claim 1.

[0016] Advantageous further developments of the invention are indicatedin the subclaims.

[0017] In accordance with a basic idea of the invention, a digitalsignal delay device is provided for converting a signal (IN) to adelayed signal (OUT) corresponding thereto, said device comprising aplurality of signal delay elements connected in series, wherein,depending on the desired delay of the delayed signal (OUT), the outputsignal of a particular signal delay element is respectively used forgenerating the delayed signal (OUT), and wherein each of the signaldelay elements comprises one single inverter only.

[0018] Depending on the respectively desired delay, the output signal ofthe respective signal delay element used for generating the delayedsignal (OUT) may then be inverted or not inverted vis-à-vis the signal(IN).

[0019] Of advantage is a development where the signal delay elements arerespectively connected with corresponding switching devices,wherein—depending on the respectively desired delay—that switchingdevice is activated that is connected with the signal delay elementwhose output signal is to be used for generating the delayed signal(OUT).

[0020] Preferably—depending on whether the output signal of a particularsignal delay element is inverted or not inverted vis-à-vis the signal(IN)—the switching device connected with the respective signal delayelement is correspondingly designed such that—on activation—it advancesthe output signal in a non-inverted or in an inverted manner.

[0021] The result is that the respectively advanced, delayed signalcorresponds to the signal (IN)—which is e.g. available at the input ofthe signal delay device—(i.e. is identical, or alternativelycomplementary thereto), and has an—adjustable—delay vis-à-vis to it(namely a delay which substantially corresponds to the delay time of theoutput signal of that signal delay element whose output signal ispossibly in inverted form—advanced via the corresponding switchingdevice.

[0022] Since the corresponding signal delay elements each only compriseone single inverter, and not e.g. two inverters connected in series, therespectively desired delay time can be adjusted substantially moreaccurately or precisely than with conventional digital signal delaydevices.

[0023] In the following, the invention will be explained in more detailby means of several embodiments and the enclosed drawing. The drawingshows:

[0024]FIG. 1 a schematic representation of a circuit arrangement of adigital signal delay device according to prior art;

[0025]FIG. 2 a schematic representation of a circuit arrangement of adigital signal delay device in accordance with an embodiment of thepresent invention;

[0026]FIG. 3 a schematic representation of an inverter circuitarrangement used as a gate of the first kind with the digital signaldelay device illustrated in FIG. 2;

[0027]FIG. 4 a schematic representation of a transfer gate circuitarrangement used as a gate of the second kind with the digital signaldelay device illustrated in FIG. 2;

[0028]FIG. 5a a schematic representation of a gate of the first kindused with an alternative embodiment of a signal delay device, and of atristate inverter additionally connected behind the respective gate ofthe first kind.

[0029]FIG. 5b a schematic representation of a gate of the second kindused with the alternative embodiment of a signal delay device, and of atristate inverter additionally connected behind the gate;

[0030]FIG. 6a a schematic representation of a gate of the first kindused with a modification of the alternative embodiment, and of atransfer gate connected therebehind, and of a tristate inverter; and

[0031]FIG. 6b a schematic representation of a gate of the first kindused with the modification of the alternative embodiment, which is usedinstead of the gate of the second kind as illustrated in FIG. 5b, and oftwo tristate converters connected therebehind.

[0032]FIG. 1 shows a schematic representation of a circuit arrangementof a digital signal delay device 1 in accordance with prior art.

[0033] The signal delay device 1 serves to apply an—adjustablyhigh—delay to a digital signal IN available at an input 2 a of thesignal delay device 1, so that a digital signal OUT which is delayedvis-à-vis the input signal IN—can be tapped at the output 2 b of thesignal delay device 1.

[0034] As is shown in FIG. 1, the signal delay device 1 comprises aplurality of signal delay elements 3 a, 3 b, 3 c, 3 d, 3 e connected inseries. The number n of signal delay elements 3 a, 3 b, 3 c, 3 d, 3 eis—as will be explained in detail below—chosen as a function of thatsignal delay that is to be obtained maximally with the signal delaydevice 1.

[0035] The first signal delay element 3 a is connected with the input 2a of the signal delay device 1 via a line 4 a, and—via a line 4 b—withthe input of the second signal delay element 3 b. The output of thesecond signal delay element 3 b is connected to the input of the thirdsignal delay element 3 c via a line 4 c. Correspondingly, the output ofthe third signal delay element 3 c is connected with the input of afurther (not illustrated) signal delay element via a line 4 d, etc.

[0036] As is further shown in FIG. 1, the input of the signal delayelement 3 d is connected to the output of a preceding (not illustrated,either) signal delay element via a line 4 e, and the input of the signaldelay element 3 e is connected to the output of the signal delay element3 d via a line 4 f.

[0037] Each signal delay element 3 a, 3 b, 3 c, 3 d, 3 e comprises twoinverters 5 a, 5 b, or 6 a, 6 b, or 7 a, 7 b, or 8 a, 8 b, or 9 a, 9 b,connected in series.

[0038] The input of the respectively first inverter 5 a, 6 a, 7 a, 8 a,9 a of each signal delay element 3 a, 3 b, 3 c, 3 d, 3 e forms therespective input of the corresponding signal delay element 3 a, 3 b, 3c, 3 d, 3 e (i.e. is connected with the corresponding line 4 a, 4 b, 4c, 4 e, 4 f), and the output of the respectively first signal delayelement inverter 5 a, 6 a, 7 a, 8 a, 9 a is connected with therespective input of the respectively second signal delay elementinverter 5 b, 6 b, 7 b, 8 b, 9 b via corresponding connecting lines 10,11, 12, 13, 14. The output of the respectively second inverter 5 b, 6 b,7 b, 8 b, 9 b of each signal delay element 3 a, 3 b, 3 c, 3 d, 3 e formsthe respective output of the corresponding signal delay element 3 a, 3b, 3 c, 3 d, 3 e (i.e. is connected with the corresponding line 4 b, 4c, 4 d, 4 f).

[0039] When the state of the signal IN available at the input of thefirst signal delay element 3 a or its first inverter 5 a, respectively,changes e.g. from “logically low” to “logically high” (—or vice versafrom “logically high” to “logically low”—), the signal at the output ofthe first signal delay element inverter 5 a (and accordingly also thesignal at the input of the second signal delay element inverter 5 b)changes—after a certain delay time t_(a)—its state from “logically high”to “logically low” (—or vice versa from “logically low” to “logicallyhigh”—). Consequently, the signal at the output of the second signaldelay element inverter 5 b or at the output of the first signal delayelement 3 a, respectively, changes—again after a certain delay timet_(b)—its state from “logically low” to “logically high” (—or vice versafrom “logically high” to “logically low”—).

[0040] The signal at the output of the second signal delay elementinverter 5 b or of the first signal delay element 3 a, respectively (andthus also the signal at the input of the second signal delay element 3 bor its first inverter 6 a, respectively) thus corresponds to the signalIN at the input of the first signal delay element 3 a or its firstinverter 5 a, respectively, with the exception that it is delayedvis-avis thereto by a—total—delay element signal delay time ofT=t_(a)+t_(b).

[0041] As has been explained above, the remaining signal delay elements3 b, 3 c, 3 d, 3 e have a structure that is correspondingly identical tothat of the first signal delay element 3 a.

[0042] Consequently—when the state of the signal available at therespective input of the respective signal delay element 3 b, 3 c, 3 d, 3e or its respectively first inverter 6 a, 7 a, 8 a, 9 a changes e.g.from “logically low” to “logically high” (—or vice versa from “logicallyhigh” to “logically low”—) again after a particular delay element(total) signal delay time T—the signal at the output of the respectivesignal delay element 3 b, 3 c, 3 d, 3 e or its respectively secondinverter 6 b, 7 b, 8 b, 9 b also changes its state from “logically low”to “logically high” (—or vice versa from “logically high” to “logicallylow”—).

[0043] The signal available e.g. at the output of the second signaldelay element 3 b (and thus also the signal at the input of the thirdsignal delay element 3 c or its first inverter 7 a, respectively) thuscorresponds to the signal IN at the input of the first signal delayelement 3 a or its first inverter 5 a, respectively, with the exceptionthat it is delayed visa-vis thereto—in total—by a total signal delaytime of T+T=2T (the signal at the output of the n-th signal delayelement thus corresponds—generally speaking—to the signal IN at theinput of the signal delay device 1, with the exception that it isdelayed vis-à-vis thereto—in total—by a total delay time of n×T).

[0044] As is further illustrated in FIG. 1, the output of the firstsignal delay element 3 a is—except that it is connected via the line 4 bwith the input of the second signal delay element 3 b-additionallyconnected via a line 15 a with the input of a first gate, e.g. atransfer gate 16 a.

[0045] Correspondingly, the outputs of the remaining signal delayelements 3 b, 3 c, 3 d, 3 e each are also connected with the input ofcorresponding further gates, in particular transfer gates 16 b, 16 d, 16e, via corresponding lines 15 b, 15 d, 15 e.

[0046] The outputs of the transfer gates 16 a, 16 b, 16 d, 16 e areconnected via corresponding lines 17 a, 17 b, 17 d, 17 e to a line 18which is connected with the output 2 b of the signal delay device 1.

[0047] Corresponding control signals C₁, C₂, . . . , C_(n−1), C_(n) areapplied to the control inputs 19 a, 19 b, 19 d, 19 e of the transfergates 16 a, 16 b, 16 d, 16 e, as will be explained in detail furtherbelow. In the case of a “logically low” control signal C₁, C₂, . . . ,C_(n−1), C_(n) the respective transfer gate 16 a, 16 b, 16 d, 16 e is ina “locked” state, and in the case of a “logically high” control signalC₁, C₂, . . . , C_(n−1), C_(n) it is in a “conductive” state. In thecase of a “conductive” state, the signal available at the input of therespective transfer gate 16 a, 16 b, 16 d, 16 e is connected through toits output (and in the case of a “locked” state disconnected from thetransfer gate output).

[0048] By the fact that respectively one of the control signals C₁, C₂,. . . , C_(n−1), C_(n) is selected such that it is in a “logically high”state, and the respective other control signals C₁, C₂, . . . , C_(n−1),C_(n) are selected such that they are in a “logically low” state, thatsignal delay element 3 a, 3 b, 3 c, 3 d, 3 e may be selected whoseoutput signal is to be connected through to the output 2 b of the signaldelay device 1.

[0049] The signal OUT that is output at the output 2 b of the signaldelay device 1 is thus applied with a delay vis-à-vis the signal at theinput 2 a of the signal delay device 1, said delay corresponding to thedelay time of the output signal of that signal delay element 3 a, 3 b, 3c, 3 d, 3 e whose output is just being connected through to the output 2b of the signal delay device 1 via the corresponding transfer gate 16 a,16 b, 16 d, 16 e (plus the delay time of the respective transfer gate 16a, 16 b, 16 d, 16 e connected through).

[0050]FIG. 2 shows a schematic representation of a circuit arrangementof a digital signal delay device 101 in accordance with an embodiment ofthe present invention.

[0051] The signal delay device 101 may e.g. be installed in a DRAMmemory element based e.g. on CMOS technology (or in any other element).It serves to apply an—adjustably high delay to a digital signal INavailable at an input 102 a of the signal delay device 101, so that adigital signal OUT delayed vis-à-vis the input signal IN—can be tappedat the output 102 b of the signal delay device 101.

[0052] As is illustrated in FIG. 2, the signal delay device 101comprises a plurality of signal delay elements 103 a, 103 b, 103 c, 103d, 103 e that are connected in series. The number n of signal delayelements 103 a, 103 b, 103 c, 103 d, 103 e is as will be explained moreexactly further below—selected as a function of that signal delay thatis to be achieved maximally with the signal delay device 101.

[0053] The first signal delay element 103 a is connected via a line 104a with the input 102 a of the signal delay device 101 and—via a line 104b—with the input of the second signal delay element 103 b. The output ofthe second signal delay element 103 b is connected to the input of thethird signal delay element 103 c via a line 104 c. Correspondingly, theoutput of the third signal delay element 103 is connected via a line 104d with the input of a further (not illustrated) signal delay element,etc.

[0054] As is further illustrated in FIG. 2, the input of the signaldelay element 103 d is connected via a line 104 e to the output of apreceding (not illustrated, either) signal delay element, and the inputof the signal delay element 103 e is connected via a line 104 f to theoutput of the signal delay element 103 d.

[0055] Each signal delay element 103 a, 103 b, 103 c, 103 d, 103 ecomprises—different from the signal delay device illustrated in FIG.1—only one single inverter 105, 106, 107, 108, 109 (instead of twoinverters connected in series), wherein the input of the respectiveinverter 105, 106, 107, 108, 109 forms the respective input of thecorresponding signal delay element 103 a, 103 b, 103 c, 103 d, 103 e(i.e. is connected with the corresponding line 104 a, 104 b, 104 c, 104e, 104 f), and wherein the output of the respective inverter 105, 106,107, 108, 109 forms the respective output of the corresponding signaldelay element 103 a, 103 b, 103 c, 103 d, 103 e (i.e. is connected withthe corresponding line 104 b, 104 c, 104 d, 104 f).

[0056] When the state of the signal IN available at the input of thesignal delay device 101 (and thus at the input of the first signal delayelement 103 a or the inverter 105, respectively) changes e.g. from“logically low” to “logically high” (—or vice versa from “logicallyhigh” to “logically low”—), the signal at the output of the first signaldelay element 103 a or of the inverter 105, respectively (andaccordingly also the signal at the input of the second signal delayelement 103 b or of the inverter 106, respectively) changes—after acertain delay time t—its state from “logically high” to “logically low”(—or vice versa from “logically low” to “logically high”—).

[0057] The signal at the output of the first signal delay element 103 aor of the inverter 105, respectively, thus corresponds to the signal INat the input of the first signal delay element 103 a or of the inverter105, respectively, with the exception that it is inverted and delayed bya delay time t vis-à-vis thereto.

[0058] When, as explained above,—after the delay time t—the signal atthe output of the first signal delay element 103 a (or of the inverter105, respectively) and accordingly also the signal at the input of thesecond signal delay element 103 b (or of the inverter 106, respectively)changes its state from “logically high” to “logically low” (—or viceversa from “logically low” to “logically high”—), the signal at theoutput of the second signal delay element 103 b or of the inverter 106,respectively, changes—again after a certain delay time t—its state from“logically low” to “logically high” (—or vice versa from “logicallyhigh” to “logically low”—).

[0059] The signal at the output of the second signal delay element 103 bor of the inverter 106, respectively, thus corresponds to the signal INat the input of the first signal delay element 103 a or of the inverter105, respectively, with the exception that it is delayed vis-à-visthereto—in total—by a delay time of t+t=2t.

[0060] As has been explained above, the remaining signal delay elements103 c, 103 d, 103 e are of a structure that is correspondingly identicalto that of the first two signal delay elements 103 a, 103 b.

[0061] Due to the respectively inverting, delayed advancement of thedigital signal that is respectively available at the input of thecorresponding signal delay element 103 c, 103 d, 103 e (as explained inanalogy above with respect to the two signal delay elements 103 a, 103b) by the respective signal delay element 103 c, 103 d, 103 e, thesignal at the output of the n-th signal delay element 103 c, 103 d, 103e thus corresponds, generally speaking, to the signal IN at the input102 a of the signal delay device 101, with the exception that it is

[0062] i) delayed vis-à-vis the signal IN by a total delay time of n×t,

[0063] and possibly—and only with such signal delay elements 103 c, 103d in which n is an odd number—that it is

[0064] ii) inverted vis-à-vis the signal IN.

[0065] As is further shown in FIG. 2, the output of the first signaldelay element 103 a or of the inverter 105, respectively, is—except thatit is connected via the line 104 b with the input of the second signaldelay element 103 b or of the inverter 106, respectively—additionallyconnected via a line 115 a with the input of a gate 116 a “of the firstkind”, as will be explained more exactly in the following.

[0066] In a correspondingly similar way is the output of the secondsignal delay element 103 b or of the inverter 106, respectively,connected via a line 115 b with the input of a gate 116 b “of the secondkind”, as will be explained more exactly in the following.

[0067] Correspondingly, the outputs of the remaining signal delayelements 103 c, 103 d, 103 e each are connected via corresponding lines115 d, 115 e with the respective input of corresponding further gates116 d, 116 e, namely, generally speaking, the respective outputs ofthose signal delay elements 103 c, 103 d in which n is an odd number areconnected with the input of a corresponding gate 116 d “of the firstkind”, and the outputs of those signal delay elements 103 c, 103 d inwhich n is an even number are connected with the input of acorresponding gate 116 e “of the second kind”.

[0068] In the present embodiment, e.g. the inverter circuit arrangement(in particular a tristate inverter circuit arrangement) illustrated indetail in FIG. 3 is e.g. used as a gate 116 a, 116 d “of the firstkind”, and the transfer gate circuit arrangement illustrated in detailin FIG. 4 is e.g. used as a gate 116 b, 116 e “of the second kind”.

[0069] As is illustrated in FIG. 4, the transfer gate circuitarrangement of the gates 116 b, 116 e “of the second kind” comprises ann-channel field effect transistor 120 a and a p-channel field effecttransistor 120 b.

[0070] The control signal C2 available at a control input 119 b of therespective gate 116 b, 116 e is—via a control line 121 a—supplied to thegate of the n-channel field effect transistor 120 a.

[0071] Furthermore, the control signal C2 available at the control input119 b of the respective gate 116 b, 116 e is additionally—via a line 121b-supplied to the input of an inverter 122, and the control signal /C2output at the output of the inverter 122 and complementary to thecontrol signal C2 is supplied to the gate of the p-channel field effecttransistor 120 b.

[0072] As is further illustrated in FIG. 4, the drains of the n- orp-channel field effect transistors 120 a, 120 b, respectively, areconnected via a line 123 with one another and additionally to the line115 b (and thus form the input of the transfer gate circuitarrangement).

[0073] Furthermore, the sources of the n- or p-channel field effecttransistors 120 a, 120 b, respectively, are connected with one anothervia a line 124, and additionally with a line 117 b that is connected toa line 118 (and thus form the output of the transfer gate circuitarrangement).

[0074] The following effect is achieved thereby: As soon as the controlsignal C2 available at the control input 119 b of the gate 116 b changesits state from “logically low” to “logically high” (and thus thecomplementary control signal /C2 changes its state from “logically high”to “logically low”), the signal available at the input of the transfergate circuit arrangement or of the gate 116 b, respectively, i.e. at theline 115 b, is connected through to the output of the transfer gatecircuit arrangement or of the gate 116 b, i.e. to the line 117 b.

[0075] When then the signal available at the control input 119 b of thegate 116 b again changes its state from “logically high” to “logicallylow” (and thus the complementary control signal /C2 changes its stateagain from “logically low” to “logically high”), the signal available atthe input of the transfer gate circuit arrangement or of the gate 116 b,respectively, i.e. at the line 115 b, is again disconnected galvanicallyfrom the output of the transfer gate circuit arrangement or of the gate116 b, respectively, i.e. from the line 117 b.

[0076] The gates 116 a, 116 d “of the first kind” have a structure thatis different from that of the gate 116 b “of the second kind”illustrated in FIG. 4. In accordance with the (tristate) invertercircuit arrangement illustrated in detail in FIG. 3, they comprise eachtwo n-channel field effect transistors 126 a, 126 b and two p-channelfield effect transistors 125 a, 125 b.

[0077] The n-channel field effect transistor 126 a and the p-channelfield effect transistor 125 a have a connection similar to aconventional, simple inverter, with the exception that the drain of then-channel field effect transistor 126 a is not directly connected to thesupply voltage, but by interconnection of the n-channel field effecttransistor 126 b, and that the drain of the p-channel field effecttransistor 125 a is not directly connected to the mass, but byinterconnection of the p-channel field effect transistor 125 b.

[0078] As is illustrated in FIG. 3, the drain of the n-channel fieldeffect transistor 126 a is—via a line 127—connected to the source of then-channel field effect transistor 126 b, and the drain of the n-channelfield effect transistor 126 b is—via a line 128—connected to the supplyvoltage.

[0079] Furthermore, the drain of the p-channel field effect transistor125 a is connected—via a line 129- to the source of the p-channel fieldeffect transistor 125 b, and the drain of the p-channel field effecttransistor 125 b is connected via a line 130—to the mass.

[0080] As is further illustrated in FIG. 3, the gates of the n- orp-channel field effect transistors 125 a, 126 a, respectively, areconnected with one another via a line 132, and are additionallyconnected to the line 115 a (and thus form the input of the (tristate)inverter circuit arrangement).

[0081] Furthermore, the sources of the n- or p-channel field effecttransistors 125 a, 126 a, respectively, are connected with one anothervia a line 131, and are additionally connected with a line 117—which isalso connected to the line 118 (and thus form the output of the(tristate) inverter circuit arrangement).

[0082] The control signal C1 available at a control input 119 a of therespective gate 116 a, 116 d is—via a control line 133 a—supplied to thegate of the n-channel field effect transistor 126 b.

[0083] Furthermore, the control signal C1 available at the control input119 a of the respective gate 116 a, 116 c is additionally supplied tothe input of an inverter 134 via a line 133 b, and the control signal/C1 that is output at the output of the inverter 134 and that iscomplementary to the control signal C1 is additionally supplied to thegate of the p-channel field effect transistor 125 b.

[0084] The following effect is achieved thereby: As soon as the controlsignal C1 available at the control input 119 a of the gate 116 a changesits state from “logically high” to “logically low” (and thus thecomplementary control signal /C1 changes its state from “logically low”to “logically high”), the n- and the p-channel field effect transistors125 b, 126 b are switched off (and thus the simple inverter formed bythe n- and the p-channel field effect transistors 125 a, 126 a isdisconnected from the supply voltage or mass, respectively, i.e.de-activated). The signal available at the input of the (tristate)inverter circuit arrangement or of the gate 116 a, respectively, i.e. atthe line 115 a, then has no influence on the signal available at theoutput of the (tristate) inverter circuit arrangement or of the gate 116a, respectively, i.e. at the line 117 a.

[0085] When the control signal C1 available at the control input 119 aof the gate 116 a then changes its state from “logically low” to“logically high” (and thus the complementary control signal /C1 changesits state from “logically high” to “logically low”), the n- and thep-channel field effect transistors 125 b, 126 b are switched on (andthus the simple inverter formed by the n- and the p-channel field effecttransistors 125 a, 126 a is connected with the supply voltage or themass, respectively, i.e. is de-activated).

[0086] Due to the two n- and p-channel field effect transistors 125 a,126 a forming a simple inverter, the signal available at the input ofthe gate 116 a, i.e. at the line 115 a, is advanced in inverted form tothe output of the gate 116 a, i.e. to the line 117 a, with therespectively one of the field effect transistors 125 a, 126 aconstituting the load resistance for the respectively other field effecttransistor 125 a, 126 a.

[0087] As is illustrated in FIG. 2, the corresponding outputs are (in acorresponding manner to the first and second gates 116 a, 116 b), alsowith the remaining gates 116 d, 116 e, connected via corresponding lines117 d, 117 e to the line 118 which is connected to the output of thesignal delay device 101.

[0088] As has already been mentioned above, corresponding controlsignals C₁, C₂, . . . , C_(n−1), C_(n) are applied to the control inputs119 a, 119 b, 119 d, 119 e of the gates 116 a, 116 b, 116 c, 116 d, 116e, namely such that respectively one of the control signals C₁, C₂, . .. , C_(n−1), C_(n) is in a “logically high” state, and the respectivelyother control signals C₁, C₂, . . . , C_(n−1), C_(n) are in a “logicallylow” state.

[0089] In this way, that signal delay element 103 a, 103 b, 103 c, 103d, 103 e may be selected whose output signal—possibly in inverted form(namely in the case of signal delay elements 103 c, 103 d where n is anodd number)—is to be connected through to the output 102 b of the signaldelay device 1.

[0090] Due to the inverted through-connection achieved by the gates 116a, 116 d and the non-inverted through-connection achieved by the gates116 b, 116 e of the signal that is output by the respectively selectedsignal delay element 103 a, 103 b, 103 c, 103 d, 103 e, it is achievedthat the signal OUT that is output at the output 102 b of the signaldelay device 101 corresponds to the signal IN at the input 102 a of thesignal delay device 101; it is, however, applied withan—adjustable—delay vis-à-vis thereto (namely with a delay correspondingto the delay time of the output signal of that signal delay element 103a, 103 b, 103 c, 103 d, 103 e whose output—possibly in inverted form—isjust being connected through via the corresponding gate 116 a, 116 b,116 d, 116 e to the output 102 b of the signal delay device 101 (plusthe delay time of the respectively active gate 116 a, 116 b, 116 d, 116e)).

[0091] The respectively desired delay time between the input signal INand the output signal OUT can be adjusted substantially more accuratelyor precisely than with the signal delay device 1 illustrated in FIG. 1(namely in time steps of a dimension of t and not in time steps of adimension of T=t_(a)+t_(b)).

[0092] In order to improve the characteristics of the signal delaydevice 101 illustrated in FIGS. 2, 3, and 4 with respect to therespectively occurring capacitive loads, in the case of an alternativeembodiment—with otherwise identical structure of the signal delay device101—in accordance with FIGS. 5a, 5 b, an additional tristate invertercircuit arrangement 135, 136 may be connected between the output of eachgate 116 a, 116 b, 116 d, 116 e (irrespective of whether “of the firstkind” or “of the second kind”) and the correspond-ng line 117 a, 117 b,117 d, 117 e corrected with the line 118.

[0093] The respectively interposed tristate inverter circuit arrangement135, 136 has a structure that corresponds to the structure of thetristate inverter circuit arrangement illustrated in FIG. 3 and actingas a gate 116 a “of the first kind” there.

[0094] By means of the interposition of the above-mentioned tristateinverter circuit arrangements 135, 136 it is achieved that the circuitsdriving the lines 118 (here: the tristate inverter circuit arrangements135, 136)—irrespective of which one of the gates 116 a, 116 b, 116 d,116 e is just activated by applying a corresponding “logically high”control signal C₁, C₂, . . . , C_(n−1), C_(n)—all have an identicalstructure, and that thus—irrespective of which one of the gates 116 a,116 b, 116 d, 116 e is activated—a respectively identical capacitiveload results.

[0095] In a modification of the above-mentioned alternative embodiment(i.e. in a further alternative embodiment), a transfer gate circuitarrangement 137 may, in accordance with FIG. 6a, be connected betweenthe output of each gate 116 a, 116 d “of the first kind” and thecorresponding additional tristate inverter circuit arrangement 135connected with the corresponding line 117 a, 117 d, wherein saidtransfer gate circuit arrangement 137 may have the same structure as thetransfer gate circuit arrangement illustrated in FIG. 4 and acting as agate 116 b “of the second kind” there.

[0096] Furthermore, in this further alternative embodiment according toFIG. 6b, the above-mentioned gates 116 b, 116 e “of the second kind” maybe replaced by corresponding gates 139 “of the first kind” (which mayhave a structure corresponding to that of the tristate inverter circuitarrangement illustrated in FIG. 3), and a respectively further tristateinverter circuit arrangement 138 (which may also have a structurecorresponding to that of the tristate inverter circuit arrangementillustrated in FIG. 3 and acting as a gate 116 a “of the first kind”there) may be connected between these gates 139 “of the first kind” andthe corresponding additional tristate inverter circuit arrangement 136connected with the respective line 117 b, 117 e.

[0097] The—interposed—transfer gate 137 illustrated in FIG. 6a may bedesigned such that the signals are advanced in such a delayed manner bythe transmission gate 137 that the—total—delay time occurring during theadvancement of the corresponding signals by the gate 116 a, the transfergate circuit arrangement 137, and the tristate inverter circuitarrangement 135 illustrated in FIG. 6a is as great as the—total—delaytime occurring during the advancement of the corresponding signals bythe gate 139, and the two tristate inverter circuit arrangements 138,136 illustrated in FIG. 6b.

1. A digital signal delay device for converting a signal (IN) into acorresponding delayed signal (OUT), comprising a plurality of signaldelay elements connected in series, wherein, as a function of thedesired delay of the delayed signal (OUT), the respective output signalof a particular signal delay element is used for generating the delayedsignal (OUT), wherein said signal delay elements each comprise onesingle inverter only.
 2. The digital signal delay device according toclaim 1, wherein as a function of the respectively desired delay, theoutput signal of the respective signal delay element used for generatingthe delayed signal (OUT) is inverted or non-inverted vis-à-vis thesignal (IN).
 3. The digital signal delay device according to claim 1,wherein said signal delay device comprising at least three signal delayelements connected in series.
 4. The digital signal delay deviceaccording to claim 3, wherein said signal delay elements arerespectively connected with corresponding gates.
 5. The digital signaldelay device according to claim 4, wherein as a function of therespectively desired delay—that gate is activated that is connected tothe signal delay element whose output signal is to be used forgenerating the delayed signal (OUT).
 6. The digital signal delay deviceaccording to claim 5, wherein, depending on whether the output signal ofa particular signal delay element is inverted or non-inverted vis-à-visthe signal (IN), the gate connected with the respective signal delayelement is designed such that it advances the output signal innon-inverted or in inverted manner.
 7. The digital signal delay deviceaccording to claim 6, wherein when the output signal of a particularsignal delay element is inverted vis-à-vis the signal (IN), the gateconnected with the respective signal delay element is designed such thatit advances the output signal in an inverted manner and, when the outputsignal of a particular signal delay element is non-inverted vis-à-visthe signal (IN), the gate connected with the respective signal delayelement is designed such that it advances the output signal in anon-inverted manner.
 8. The digital signal delay device according toclaim 6, wherein when the output signal of a particular signal delayelement is inverted vis-à-vis the signal (IN), the gates connected withthe respective signal delay element is designed such that it advancesthe output signal in a non-inverted manner and, when the output signalof a particular signal delay element is non-inverted vis-à-vis thesignal (IN), the gate connected with the respective signal delay elementis designed such that it advances the output signal in an invertedmanner.
 9. The digital signal delay device according to claim 8, whereinthe gate, depending on whether they are connected with a signal delayelement whose output signal is inverted or non-inverted vis-à-vis thesignal (IN)—comprise an inverter circuit arrangement or a transfer gatecircuit arrangement.
 10. The digital signal delay device according toclaim 8, wherein the gates, depending on whether they are connected witha signal delay element whose output signal is inverted or non-invertedvis-à-vis the signal (IN)—comprise two inverter circuit arrangements, ora transfer gate circuit arrangement and an inverter circuit arrangement.11. The digital signal delay device according to claim 8, wherein thegates, depending on whether they are connected with a signal delayelement whose output signal is inverted or non-inverted vis-à-vis thesignal (IN)—comprise two inverter circuit arrangements and a transfergate circuit arrangement, or three inverter circuit arrangements. 12.The digital signal delay device according to claim 11, wherein at leastone of the inverter circuit arrangements is a tristate inverter circuitarrangement.
 13. The digital signal delay device according to claim 2,wherein said signal delay device comprising at least three signal delayelements connected in series.
 14. The digital signal delay deviceaccording to claim 13, wherein said signal delay elements arerespectively connected with corresponding gates; wherein as a functionof the respectively desired delay—that gate is activated that isconnected to the signal delay element whose output signal is to be usedfor generating the delayed signal (OUT); and wherein, depending onwhether the output signal of a particular signal delay element isinverted or non-inverted vis-à-vis the signal (IN), the gate connectedwith the respective signal delay element is designed such that itadvances the output signal in non-inverted or in inverted manner. 15.The digital signal delay device according to claim 14, wherein when theoutput signal of a particular signal delay element is inverted vis-à-visthe signal (IN), the gate connected with the respective signal delayelement is designed such that it advances the output signal in aninverted manner and, when the output signal of a particular signal delayelement is non-inverted vis-à-vis the signal (IN), the gate connectedwith the respective signal delay element is designed such that itadvances the output signal in a non-inverted manner.
 16. The digitalsignal delay device according to claim 14, wherein when the outputsignal of a particular signal delay element is inverted vis-à-vis thesignal (IN), the gates connected with the respective signal delayelement is designed such that it advances the output signal in anon-inverted manner and, when the output signal of a particular signaldelay element is non-inverted vis-à-vis the signal (IN), the gateconnected with the respective signal delay element is designed such thatit advances the output signal in an inverted manner.
 17. The digitalsignal delay device according to claim 16, wherein the gate, dependingon whether they are connected with a signal delay element whose outputsignal is inverted or non-inverted vis-à-vis the signal (IN)—comprise aninverter circuit arrangement or a transfer gate circuit arrangement. 18.The digital signal delay device according to claim 16, wherein thegates, depending on whether they are connected with a signal delayelement whose output signal is inverted or non-inverted vis-à-vis thesignal (IN)—comprise two inverter circuit arrangements, or a transfergate circuit arrangement and an inverter circuit arrangement.
 19. Thedigital signal delay device according to claim 16, wherein the gates,depending on whether they are connected with a signal delay elementwhose output signal is inverted or non-inverted vis-à-vis the signal(IN)—comprise two inverter circuit arrangements and a transfer gatecircuit arrangement, or three inverter circuit arrangements.
 20. Thedigital signal delay device according to claim 19, wherein at least oneof the inverter circuit arrangements is a tristate inverter circuitarrangement.